1. Field of the Invention
The invention relates to an electro-luminescence display device, and more particularly, to a current-driven type electro-luminescence display device.
2. Description of the Related Art
Various flat panel display devices having a lightweight and a compact size have replaced a cathode ray tube (CRT). The flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an electro-luminescence (EL) display, an organic light emitting display (OLED) and so on.
The OLED is classified into a passive matrix and an active matrix. The active matrix OLED includes a thin film transistor, whereas the passive matrix has no thin film transistor. The active matrix OLED (AMOLED) is more suitable for a display device having a large size and a high resolution. The OLED is a self-luminous display device which electrically excites a fluorescent organic compound to emit light. It operates at low voltage and is thinner than other flat display devices. Further, the OLED has excellent characteristics such as a wide viewing angle and a rapid response speed. The OLED is currently in use for various devices, such as a hand phone, a car navigation, a hand PC and etc.
FIG. 1 is a circuit diagram illustrating a pixel structure of a current-driven type electro-luminescence display device of the related art. Referring to FIG. 1, the current-driven type electro-luminescence display device 100 includes an electro-luminescence (“EL”), a switch part 10 and a data line. The EL forms a pixel in accordance with the current strength. The switch part 10 includes switches S/W1, S/W2 and S/W3 and controls the current supplied to the EL. The data line DATA and first and second scan lines Scan1, Scan2 supply a signal to the switch part 10.
The first switch S/W1 includes a drain that is connected to the data line DATA and a gate that is connected to the first scan line Scan1. The second switch S/W2 has a gate that is connected to the first scan line Scan1 and a drain that is connected to a source of the first switch S/W1. A storage capacitor Cstg is arranged between a high potential voltage VDD and a source of the second switch S/W2. A drive transistor D-TFT has a gate that is connected between the storage capacitor Cstg and the source of the second switch S/W2 and a source that is connected to the high potential voltage VDD. The third switch S/W3 includes a gate that is connected to the second scan line Scan2 and the source is connected to a drain of the drive transistor D-TFT. The EL is connected between a drain of the third switch S/W3 and a ground GND.
FIG. 2 illustrates a drive waveform for the electro-luminescence display device 100 of FIG. 1. In an interval A of FIG. 2, a low voltage applies to the first scan line Scan1. The first switch S/W1 and the second switch S/W2 are turned on. When the first and second switches S/W1, S/W2 are turned on, the drive transistor D-TFT forms a diode connection. The current sinks to the data line DATA through the drive transistor D-TFT.
In an interval B, the first and second switches S/W1 and S/W2 are turned-off and the drive transistor D-TFT is turned on by a storage capacitor Cstg. The third switch S/W3 is turned on with a low voltage supplied to the second scan line Scan2 so that a current corresponding to a designated data value flows in the EL for one frame period.
FIG. 3 illustrates parasitic capacitors which are hidden in the electro-luminescence display device 100. A first parasitic capacitor C1 is formed between the gate and source of the second switch S/W2. A second parasitic capacitor is formed between the source of the second switch S/W2 and the source of the third switch S/W3. A third parasitic capacitor C3 is formed between the gate and the source of the third switch S/W3. Due to the influence of the parasitic capacitors C1, C2 and C3, when the first switch and the second switch S/W1, S/W2 are turned off, a DC voltage offset is generated and a kickback effect occurs. The kickback effect occurs in particular where the first and second switches S/W1, S/W2 are turned off and the third switch S/W3 is turned on.
Referring to FIG. 4, a kickback voltage develops in the first parasitic capacitor C1 by as much as ΔVp1 in a direction of increasing the gate voltage of the drive transistor D-TFT. A kickback voltage also develops in the third parasitic capacitor C3 by as much as ΔVp2 in a direction of decreasing the gate voltage of the drive transistor D-TFT. As a result, the kickback voltage may not be entirely cancelled and a voltage difference by “D” is generated. The voltages ΔVp1 and ΔVp2 are computed with the following equation (2):
                              Δ          ⁢                                          ⁢          Vp          ⁢                                          ⁢          1                =                                            C              ⁢                                                          ⁢              1                                                      C                ⁢                                                                  ⁢                1                            +                              C                ⁢                                                                  ⁢                2                            +                              C                ⁢                                                                  ⁢                3                            +              Cstg                                ×          Δ          ⁢                                          ⁢          Vgs          ⁢                                          ⁢          1                                    (                  Equation          ⁢                                          ⁢          1                )                                          Δ          ⁢                                          ⁢          Vp          ⁢                                          ⁢          2                =                                                            C                ⁢                                                                  ⁢                2                            +                              C                ⁢                                                                  ⁢                3                                                                    C                ⁢                                                                  ⁢                1                            +                              C                ⁢                                                                  ⁢                2                            +                              C                ⁢                                                                  ⁢                3                            +              Cstg                                ×          Δ          ⁢                                          ⁢          Vgs          ⁢                                          ⁢          3                                    (                  Equation          ⁢                                          ⁢          2                )            where ΔVgs1 is a change amount of a threshold voltage between the gate and the source of the first switch S/W1, and ΔVgs3 is a change amount of a threshold voltage between the gate and the source of the third switch S/W3.
The kickback effect may result in a non-uniformity of a picture quality. A displayed picture appears inconsistent and uneven in accordance with its characteristics. Accordingly, there is a need of a current-driven type electro-luminescence display device which provides an improved uniformity of a picture quality.